The present invention relates to a delay circuit for a digital signal suitable for an integrated circuit, in particular, relates to such a delay circuit which is free from temperature variation, power supply voltage variation and/or variation of the production process. The delay time in the present delay circuit is obtained by charging and/or discharging a capacitor through a current source which uses a MOS field effect transistor (FET) to generate a ramp voltage, and determining the delay time by the time until said ramp voltage reaches a threshold level of a logic circuit.
A delay circuit for delaying a digital signal by a predetermined time is essential in a digital circuit field including a personal computer, and/or a digital measurement apparatus, for adjusting the timing of control signals.
Conventionally, a delay circuit has been implemented by using a hybrid IC circuit having an LC delay element and a logic gate for input/output buffer. However, a delay circuit in the form of a monolithic IC has been desired for producing a miniaturized and/or low cost device.
A delay circuit which is suitable for a monolithic integrated circuit has been known by charging or discharging a capacitor through a current source with a MOS field effect transistor to generate a ramp voltage, and the delay time is defined by the time until the ramp voltage reaches a threshold level of a logic circuit.
FIG. 12 shows a circuit diagram of a prior delay circuit which uses a ramp voltage. In the figure, the symbol M.sub.1 is a first MOS field effect transistor, M.sub.2 is a second MOS field effect transistor, C is a capacitor, Q.sub.1 is a logic circuit, V.sub.BIAS is DC bias potential, V.sub.DD is DC power supply voltage, V.sub.IN is an input terminal of a digital signal which is subject to delay, and V.sub.OUT is an output terminal of a delayed signal.
In the above embodiment, the first MOS field effect transistor M.sub.1 which is a P channel element, has a gate G.sub.1 which is coupled with an input terminal V.sub.IN, and, a source S.sub.1 which is coupled with power supply voltage V.sub.DD. The second MOS field effect transistor M.sub.2 which is N channel element has a drain D.sub.2 which is connected to the drain D.sub.1 of the first transistor M.sub.1, and the source S.sub.2 which is grounded. The gate G.sub.2 of the second transistor M.sub.2 receives the DC (direct current) bias voltage V.sub.BIAS. The capacitor C is coupled between the point (a) which is junction point of the drains D.sub.1 and D.sub.2 of two transistors, and the ground. The logic circuit Q.sub.1 is coupled with the point (a), and provides a logic output signal depending upon the charge in the capacitor C to provide the delayed output signal V.sub.OUT. The logic circuit Q.sub.1 in the embodiment is implemented by an inverter, which provides low level output when the potential of the point (a) is higher than the threshold level of the inverter, and provides high level output when the potential of the point (a) is lower than said threshold level.
FIG. 13 shows the operational waveforms of the circuit. When an input digital signal V.sub.IN is in low level, both the transistors M.sub.1 and M.sub.2 are active, and the potential on the point (a) is determined by the divisional ratio of the power potential V.sub.DD by two transistors M.sub.1 and M.sub.2. When the ratio (W/L) of the gate width W to the channel length L of the first transistor M.sub.1 is considerably large as compared with that of the second transistor M.sub.2, the potential at the point (a) is at high level as shown in FIG. 13(b), and the potential is approximately V.sub.DD. The voltage between the gate and the source of, the first transistor M.sub.1 is larger than that of the second transistor M.sub.2.
When the digital input signal V.sub.IN changes to high level at time t.sub.0 as shown in FIG. 13(a), the first transistor M.sub.1 becomes to cutoff state, and therefore, the charge on the capacitor C begins to discharge through the second transistor M.sub.2. The gate G.sub.2 of the second transistor M.sub.2 receives the DC bias voltage V.sub.BIAS, and it functions as a constant current source in the saturation region where the following equation is satisifed. EQU V.sub.DS .ltoreq.V.sub.GSN -V.sub.TN
where V.sub.DS is the voltage between the drain and the source, V.sub.GSN is equal to V.sub.BIAS, and V.sub.TN is the threshold voltage.
Accordingly, when the digital input signal V.sub.IN changes to high level, the potential at the point (a) decreases with approximate linearly as shown in FIG. 13(b).
The potential on the point (a) is monitored by a logic circuit Q.sub.1 which is implemented by an inverter, which changes the output signal V.sub.OUT from low level to high level as shown in FIG. 13(c), when the input voltage reaches the threshold voltage V.sub.TH at time t.sub.1.
The delay time T.sub.d is the duration between the rising edge of the digital input signal V.sub.IN and the rising edge of the output signal of the inverter Q.sub.1.
The delay time T.sub.d is shown by the following equation. EQU T.sub.d =(V.sub.DD -V.sub.TH).multidot.C/I.sub.DN
where T.sub.TH which is the threshold voltage of the logic circuit Q.sub.1, and is expressed as follows provided that the logic circuit Q.sub.1 is implemented by a CMOS inverter. EQU V.sub.TH =(.beta.V.sub.DD +.beta.V.sub.TP +V.sub.TN)/(1+.beta.) EQU .beta.=[(L.sub.n .multidot.W.sub.p .multidot..mu..sub.p)/L.sub.p .multidot.W.sub.n .multidot..mu..sub.n)].sup.1/2
where V.sub.TN (positive), L.sub.n, and W.sub.n are the threshold voltage, channel length, and the gate width, respectively, of the N-channel element which constitutes a CMOS inverter, .mu..sub.n is a mobility of an electron which is a carrier in an N-channel element, V.sub.TP (negative), L.sub.p, and W.sub.p are the threshold voltage, the channel length, and the gate width, respectively, of the P-channel element which constitutes a CMOS inverter, and .mu..sub.p is the mobility of a positive hole which is the carrier in a P-channel element.
It should be noted in the above equations that the threshold voltage V.sub.TH depends upon the source voltage V.sub.DD. For instance, when .beta.=1, V.sub.TN =.vertline.V.sub.TP .vertline., then T.sub.TH =0.5V.sub.DD.
Further, I.sub.DN in said equation for providing the delay time T.sub.d is the drain current of the second transistor M.sub.2, and is approximately obtained by the following equation. EQU I.sub.DN =(W.sub.N /L.sub.N)(.mu..sub.N C.sub.0 /2)(V.sub.GSN -V.sub.TN).sup.2
where V.sub.TN, L.sub.N and W.sub.N are the threshold voltage, the channel length and the gate width, respectively, of the second transistor M.sub.2, .mu..sub.N is the mobility of an electron which is the carrier of the second transistor M.sub.2, C.sub.0 is the gate capacity for unit area of the second transistor M.sub.2.
However, a prior delay circuit as described in FIGS. 12 and 13 has the following disadvantages.
a) As apparent in said equation of I.sub.DN, when the carrier mobility .mu..sub.N changes, the drain current I.sub.DN changes, and then, the delay time T.sub.d changes. The carrier mobility .mu..sub.N becomes small when the temperature becomes high. Therefore, the delay time T.sub.d becomes longer depending upon the temperature rise.
b) As apparent from the equation for the threshold voltage V.sub.TH, the threshold voltage V.sub.TH changes depending upon the channel length L.sub.p or L.sub.n, the gate width W.sub.p or W.sub.n, the mobility .mu..sub.n or .mu..sub.p, and the threshold voltage V.sub.Tn or V.sub.Tp, because of the change of the manufacturing process condition.
Further, as apparent from the equation of I.sub.DN, the drain current I.sub.DN of the second transistor M.sub.2 changes, depending upon the channel length L.sub.N, the gate width W.sub.N, the gate capacity C.sub.0, and the threshold voltage V.sub.TN because of the manufacturing process change. Thus, the delay time depends upon the error in the production process of transistors.
c) As apparent from the equation of T.sub.d, the delay time T.sub.d is proportional to (V.sub.DD -V.sub.TH) which is the difference between the power voltage V.sub.DD and the threshold voltage V.sub.TH of an inverter, the delay time depends upon the power supply voltage V.sub.DD.